Radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) device is a new generation integrated solid microwave power semiconductor device. It is a product of the combination of semiconductor integrated circuit technology and microwave electronics technology and has a variety of advantages such as high linearity, high gain, high voltage endurance, great output power, good thermal stability, high efficiency, good broadband matching property and high compatibility with MOS technology. Moreover, it is commercially available at a much lower price than gallium-arsenide (GaAs) devices. All of these advantages make the RF LDMOS device a very competitive power device that has been widely used as a power amplifier for Global System for Mobile communications (GSM), Personal Communications Service (PCS) and Wideband Code Division Multiple Access (W-CDMA) base stations and in wireless broadcasting, nuclear magnetic resonance (NMR) and many other applications.
Breakdown voltage (BV) and on-resistance Rdson are two key feature parameters for characterizing the performance of an RF LDMOS device. A high breakdown voltage ensures a high operational stability for the device. For example, an RF LDMOS having a working voltage of 50 V is typically required to have a breakdown voltage of not lower than 110 V. Moreover, the on-resistance Rdson of a RF LDMOS device is directly related to its output power, gain and other properties.
FIG. 1 shows a common RF LDMOS device. In the device, a p-type substrate 1 is covered by a p-type epitaxial 10. A p-type well 11 is formed in a left portion of the p-type epitaxial 10, and a lightly doped n-type drain region 12 is formed in a right portion of the p-type epitaxial 10. The p-type well 11 is not in contact with the lightly doped n-type drain region 12.
Moreover, a heavily doped n-type source region 24 is formed in an upper portion of the p-type well 11.
A heavily doped n-type drain region 21 is formed in a right portion of the lightly doped n-type drain region 12.
Both the heavily doped n-type source region 24 and the heavily doped n-type drain region 21 have a higher n-type dopant concentration than the lightly doped n-type drain region 12.
A contact column 13 is connected to a left edge of the p-type well 11.
The contact column 13 is further extending downwards into the p-type substrate 1.
A heavily doped p-type region 22 is formed in an upper portion of the p-type well 11 left to the heavily doped n-type source region 24. The heavily doped p-type region 22 is connected to the contact column 13 and has a higher p-type dopant concentration than the p-type well 11.
A gate oxide layer 14 is covering both an upper portion of the p-type well 11 right to the heavily doped n-type source region 24 and a portion of the p-type epitaxial 10 between the p-type well 11 and the lightly doped n-type drain region 12.
A polysilicon gate 15 is covering the gate oxide layer 14.
An oxide layer 16 is covering both the polysilicon gate 15 and a left portion of the lightly doped n-type drain region 12.
Furthermore, a right portion of the oxide layer 16 is covered by a Faraday shield 17.
In the RF LDMOS device with such a structure, the lightly doped n-type drain region 12 is generally formed in one single doping step. As the lightly doped n-type drain region 12 has a low dopant concentration, it can result in a high breakdown voltage BV. However, conflictingly, the low dopant concentration also leads to a great on-resistance Rdson.